The present invention relates to a manufacturing process for a small-sized and thin type semiconductor package. More particularly, to a manufacturing process for a semiconductor package by which an circuit substrate will not be wasted and which allows a plurality of packages to be taken from the substrate thereby having the highly productivity and to an circuit substrate aggregation or assembly used for manufacturing such packages.
As a semiconductor package becomes smaller and more integrated, the flip-chip bonding method has been developed wherein a bare chip is directly mounted on a substrate with its face directed downward. More recently, a variety of portable tools such as a VTR having a camera integrated thereinto and a personal handy telephone is appearing into the market one after another and such a portable tool has a package as small as a bare chip integrated therein, namely a chip size/scale package (CSP). Because of such a situation, CSP""s are strongly needed in the market, thereby the development of CSP""s recently is under accelerating.
In manufacturing circuit board aggregation or assembly 100 at a manufacturer""s site, a roll of 1 m wide glass filler sheet having a resin impregnated thereinto is cut in accordance with a standard size of 1 mxc3x971 m or 1 mxc3x971.2 m. Then, a copper film is laminated onto the both sides of the standardized sheet, which will be pressed into an original substrate. The original substrate is further cut into substrate materials with a convenient and readily usable size.
In FIG. 20, a plan view of substrate material 110 is shown. This substrate material is obtained by cutting an original sheet with a standard size into nine pieces. Substrate material 110 measures 330 mm wide (W) and 330 mm long (L). For example, ten (10) strips of circuit board aggregation 100 will be obtained by cutting this substrate material 110. Each circuit substrate aggregation is, for example, 56 mm wide (W1) and 115 mm long (L1). Each circuit substrate aggregation 100 is, as illustrated in FIG. 20, arranged as two vertical rows X and five horizontal columns.
In FIG. 21, an example of circuit substrate aggregation 100 is shown. The circuit substrate aggregation has a blank area (margins) for manufacturing packages along the perimeter. In particular, the substrate has a b1 wide (for example 5 mm) manufacturing blank area along the vertical perimeter and b2 wide (for example 7 mm) manufacturing blank area along the horizontal perimeter.
In the area surrounded by the manufacturing blank area of the circuit substrate aggregation 100, cut lines 2 are formed in the X and Y directions which are perpendicular to each other so as to form a plurality of individual circuit substrate 1 to be obtained by cutting it. From circuit substrate aggregation 100 as shown in FIG. 21, fifty-five (=5xc3x9711) circuit substrates having the size of 9 mmxc3x979 mm can be obtained.
A conventional manufacturing process for CSP type semiconductor packages will now be briefly explained by referring to FIGS. 22A to 23Cxe2x80x2. In FIGS. 22A-22C and FIGS. 23A-23C, respectively, top plan views are shown in the right side of the figures while cross-sectional views obtained by cutting the top plan views along the cutting lines are shown in the left side. In the example of FIGS. 22A to 23Cxe2x80x2, four circuit substrates are illustrated to be taken.
A conventional process for manufacturing semiconductor packages includes the steps for forming a circuit substrate (FIG. 22Axe2x80x2), mounting IC chips onto the substrate (FIG. 22Bxe2x80x2), encapsulating the mounted chips with resin (FIG. 22Cxe2x80x2), attaching standard member on the encapsulated (sealing) chips (FIG. 23Axe2x80x2), dicing the chips (FIG. 23Bxe2x80x2) and forming electrodes on the chips (FIG. 23Cxe2x80x2).
In manufacturing semiconductor packages, through-holes (not shown) are formed on the circuit substrate aggregation 100, both surfaces of which are copper laminated in the step of forming the circuit substrate.
Then, on the both surfaces of this circuit substrate aggregation 100, copper-plated layers are formed by means of electroless copper plating and electro copper plating. Further, the copper-plated layers are laminated with etching resist, which will be sequentially exposed to light and developed to form pattern masks. Thereafter, the copper-plated layers are subjected to pattern etching via the pattern masks by using etching solution. Through this pattern etching process, several sets of IC connecting electrodes (bonding pattern) 3 for a plurality of chips are formed on the upper surface of circuit substrate aggregation 100 and external connection electrodes 4, which are pad electrodes arranged in a matrix, are formed on the bottom side, respectively.
Next, a solder resist processing follows, thereby forming a resist film on the bottom side of circuit substrate aggregation 100. This resist film has openings where external connection electrodes 4, which are the solderable region, are exposed. By forming this resist film in this way, the bottom surface of integrated surface 100 will be planarized. Thus, the circuit substrate aggregation is completed wherein a number of same-shaped platable regions are arranged on the bottom surface in a matrix manner (FIGS. 22A and 22Axe2x80x2).
In the next step of mounting the IC chips on the substrate, solder bumps 5 are formed on the pad electrode of the IC wafer (not shown). The process for forming solder bumps 5 includes the stud bump method, ball bump method and plated bump method. The plated bump method among these is suitable for miniaturizing the IC chips because it allows the bumps to be formed in a narrow space between the pad electrodes.
Then, the IC wafer on which the solder bumps are formed is cut into chips of a predetermined size while being attached on a adhesive tape, to thereby form the IC chips 6. In this cutting process, the full-cut scheme is employed in cutting the wafer in the X and Y directions with an apparatus such as a dicing saw. After the wafer is cut, IC chips 6 on the adhesive tape are separated into a plurality of individual units.
Next, flux (not shown) is applied onto a predetermined location of either the solder bumps of the divided IC chips or IC connecting electrodes 3 formed on the upper surface of circuit substrate aggregation 100. When this is completed, IC chips 6 are mounted on the main surface of circuit board aggregation 100 in such a manner that one chip is mounted on a single circuit substrate. The surface of IC chip 6 on which solder bumps 5 are formed is opposed against the upper side of the circuit substrate aggregation and solder bumps 5 are positioned on IC connecting electrodes 3. Then, IC connecting electrodes 3 are electrically connected to IC chips 6 by means of a solder reflow processing. As described above, IC chips 6 (flip-chips) are mounted onto circuit board aggregation 100 (FIGS. 22B and 22Bxe2x80x2).
In the next encapsulation step, a plurality of IC chips 6 is integrally encapsulated using a thermosetting resin 7 by performing a side-potting across the adjacent IC chips 6. In such a manner, the same IC chips 6 are secured on each circuit substrate 1 of the circuit substrate aggregation 100 with the face down direction as shown in FIGS. 22C and 22Cxe2x80x2.
In the next step of attaching a standard member, the planar bottom surface of the circuit substrate aggregation on which the IC chips are mounted is attached to standard member 8 by using a adhesive or a PSA (pressure-sensitive adhesive) tape. The adhesion between circuit substrate aggregation 100 and standard member 8 is secured because both of the attached surfaces are planar (FIGS. 23A and 23Axe2x80x2).
In the next dicing step, as shown in FIGS. 23B and 24Bxe2x80x2, circuit substrate aggregation 100 is cut with a cutting device such as a dicing saw along the cut lines formed on the circuit substrate aggregation in the X and Y directions and the cut circuit substrate 1 is separated into individual circuit substrates 1 Here a dicing machine DFD-640 (product name) equipped with a dicing blade NBC-ZB1090S3 (product name) both manufactured by Disco Corporation is used in this cutting process.
After the dicing step, circuit substrates 1 are detached from standard member 8 by dissolving the adhesive and the like with a solution.
In the next step of forming the electrodes, solder balls are attached to external connection electrodes 4 formed on the bottom surface of the individual circuit substrate. Then, the solder balls are subjected to a reflow process and ball electrodes are formed.
In the above described steps, the formation of individual flip-chip BGA""s (ball grid arrays) 200 is completed.
However, the above described process for manufacturing the semiconductor packages suffers from the following problems. In the conventional method, the solder ball electrodes are individually formed on a single circuit substrate already diced from the integrated semiconductor substrates. Thus, in a small package CSP, the distance between the perimeter of the circuit substrate and the center of the solder ball electrode positioned most adjacent to the perimeter tends to be small, so that it will be difficult to maintain the blank area reserved to secure an apparatus for attaching the solder balls in the step of forming the solder balls. Further, since the solder balls are attached to each of the single circuit substrates, the productivity of this method is low, so that the manufacturing cost increases.
Also, the conventional circuit board aggregation have further problems. As small portable devices are required to be miniaturized, the packages have been strongly requested to be miniaturized and made thinner as well as to lower the manufacturing cost of the packages as much as possible. Since blank areas are reserved for manufacturing purposes, the number of the circuit substrates to be taken therefrom tends to be small. For example, when the blank area b2 along the horizontally oriented F1 is 7 mm wide, the total width of the two blank areas for manufacturing purposes along the both sides will be 14 mm, which is equal to more than one row of circuit substrate 1 which is 9 mmxc3x979 mm. If all the blank areas are eliminated from circuit substrate aggregation 100 as shown in FIG. 21, as many as sixty circuit substrates, each having an area of 9 mmxc3x979 mm, can be taken from the substrate. In reality, however, only 55 circuit substrates 1 may be taken because there exist blank areas. Therefore, about 9% of the circuit substrate will be wasted.
Accordingly, it would be appreciated from the above context that an object of the present invention is to provide a circuit board aggregation or assembly, the productivity of which is high and thus which may be preferably used to manufacture semiconductor substrates at a low cost.
The process for manufacturing a semiconductor package with mounted IC chips of the present invention comprises,
a circuit board fabricating step for forming a plurality of bonding patterns for mounting IC chips on a main surface of a circuit board aggregation or assembly which can be divided into a plurality of circuit boards, and forming a plurality of electrode patterns for external connection on the back of this circuit board aggregation,
an IC chip mounting step for mounting IC chips on each circuit board of the main surface of the circuit board aggregation and electrically connecting the bonding patterns and IC chips,
a sealing step for sealing the IC chips with a sealing resin,
an electrode forming step for providing projections on the electrode patterns for external connection,
an attaching step for causing the package aggregation unit fabricated by the circuit board fabricating step, IC chip mounting step, sealing step, and electrode forming step to be affixed to a standard member, and
a cutting step which comprises cutting the attached package aggregation unit into each circuit board, thereby obtaining a plurality of semiconductor packages each including one circuit board.
In the present invention, since the cutting step follows the electrode forming step, electrodes having the projections can be formed on all circuit boards of the circuit board aggregation at the same time. This ensures the high productivity and the reduction of the production costs.
In addition, since the electrodes having the projections are simultaneously formed on each circuit board of the circuit board aggregation, the margin for the fabrication of the circuit board aggregation can be used as the margin for a solder ball on anchoring a jig in the electrodes having projection forming step.
Accordingly, a reliable, highly productive, and inexpensive process for manufacturing the semiconductor packages which is suitable for mounting on small portable equipment can be provided by the present invention.
In the process for manufacturing the semiconductor packages of the present invention, a spacer can be provided on the area from which the circuit board packages are separated such as a margin for fabrication. If the area to be separated is secured to the standard member through this spacer, pieces in the separation area can be prevented from jumping up and down in the dicing machine during the cutting operation. As a result, damage of the dicing blades and IC chips can be prevented.
Moreover, the circuit board aggregation of the present invention is provided with the margins for fabrication only along the peripheries of two opposing sides out of four sides of the quadrilateral surrounding the circuit board aggregation. This enables a greater number of circuit boards to be made from the circuit boards aggregation.
Accordingly, a circuit board aggregation which is suitable for the manufacture of the semiconductor packages inexpensively and with high productivity can be provided by the present invention.
Moreover, the manufacturing process can be automated and productivity of the circuit board aggregation can be further improved by providing the substrate with a width (W) equivalent to a common length (A) which satisfies the following conditions. Specifically, a length MI obtained by dividing the original length (L) of one side of a specified size substrate by K1 (M1=L/K1) and a length M2 obtained by dividing the original length (L) by K2 (M2=L/K2) are respectively a product of the common length (A) multiplied by an integer. This substantially reduces the production costs for the circuit board aggregation of the present invention, which results in a decrease in manufacturing costs of the semiconductor packages.